The invention relates in general to timing recovery, and in particular, to an initial phase for a timing recovery circuit.
Timing recovery synchronizes data in an input signal and a local sampling signal associated with a sampling frequency and a sampling phase. Locking the sampling frequency involves estimating the data period, such that samples can be taken at a correct rate without losing data. Locking the sampling phase requires evaluating the correct time within a data period to take a sample. Data typically peaks at the center of a data period, with sampling thereof providing optimum signal to noise ratio (SNR) and more robust transmission. Consequently, timing recovery is commonly realized by altering the sampling frequency and the sampling phase such that the input signal is sampled at the peak.
Timing recovery schemes rely on sampling of the input signal close to the data peak with the sampling signal to yield a train of sample data, from which is generated a series of timing errors tracking both sampling frequency and phase errors for correction of the sampling signal. A requirement for fast convergent and accurate sampling signal is to sample as close to data peak as possible. If the input signal is sampled at data transition, the timing recovery scheme cannot evaluate the timing error correctly, such that the sampling signal cannot reach convergence rapidly.
FIG. 1 is a block diagram of a conventional timing recovery circuit, in which timing recovery circuit 1 comprises Analog to Digital (AD) converter 10, Mueller and Muller timing recovery controller 12, phase generator 14, slicer 16 and equalizer output 18.
Both Mueller and Muller timing recovery controller 12 and phase generator 14 are coupled to AD converter 10, which receives input signal Sin, samples input signal Sin with sampling signal Ssp from phase generator 14, and renders a series of sample data Di to Mueller and Muller timing recovery controller 12, together with hard decision data Dh from slicer 16 produces timing error Te controlling phase generator 14, such that the phase of sampling signal Ssp is synchronized with the data in input signal Sin, and the data peaks are sampled at AD converter 10. After equalization is stable, Mueller and Muller timing recovery controller 12 switches to equalizer output 18 to replace slicer 16 for hard decision data Dh.
Upon initialization of the timing recovery process, phase generator 14 delivers sampling signal Ssp with an arbitrary phase selection to AD converter 10. If the arbitrary phase is close to the transient edge of the data, false sample data Di may be taken and directed to Mueller and Muller timing recovery controller 12, which in turn produces inaccurate timing error Te and brings slow convergence to the data synchronization.
Thus a method and circuit for timing recovery with an initial phase is proposed.